Download Trace Theory for Automatic Hierarchical Verification of by David L. Dill PDF

By David L. Dill

Speed-independent circuits provide a possible option to the timing difficulties of VLSI. during this ebook David Dill develops and implements a thought for sensible computerized verification of those regulate circuits. He describes a proper version of circuit operation, defines the correct courting among an implementation and its specification, and constructs a working laptop or computer software which can cost this relationship.Asynchronous or speed-independent circuit layout has won renewed curiosity within the VLSI neighborhood a result of probabilities it offers for facing difficulties that come up with the expanding complexity of VLSI circuits. Speed-independent circuits provide a fashion round such phenomena as clock skew, that are a significant predicament within the layout of huge platforms. they could expedite circuit layout by means of decreasing layout time and simplifying the final process.A significant problem to the winning usage of speed-independent circuits is correctness. The verification technique defined the following insures layout is right and since it may be automatic it's a major virtue over handbook verification. Dill proposes specific theories - prefix-closed hint buildings, that may version and specify protection homes, and entire hint buildings, which may additionally care for liveness and equity properties.David L. Dill bought his doctorate from Carnegie Mellon college and is Assistant Professor within the desktop technological know-how division at Stanford college. hint concept for computerized Hierarchical Verification of velocity autonomous Circuits is a 1988 ACM exceptional Dissertation

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Extra resources for Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits

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4. 9. If X � A· and X' � (A u D'r where D' n A = 0, then X n del(D')(X') = del(D')[del(D')-l(X) n X'). del(D')[del(D')-I(X»). 5. we can conclude abat del(D')[del(D')-l{X)nX'] is a subset of X n del(D ')(X'). To see inclusion in abe other direction, suppose x is any sequence in X n del(D')(X'). Then x E X and abere is ayE X' such that x = del(D')(y). But then y E deJ(D')-I(X).

They have defined a selectiOn/resolution model. which represents processes as generalized finite-state automata. The method allows all safety properties and mnny liveness properties to be checked. Several realistic and quite complex examples have bee n verified us i ng this system. Introduction 16 Judging from results on real examples , harder problems than those of Holzmann global state graphs . 9. Summary There are some general observations to be made about the applicability of existing work to our problcm.

D"[(c,I),a] = [n'(e, a), 11 when n'(e,a) E N'. n"[(c,O),a] = o(c,a) when n(c, a) E A. and D" [(C, 1), a] = n'(c, a) when n'(c, a) E A'. In the first two cases, the original mappings of pins to nodes is preserved (no new connections are fonned). In the second two cases, new connections can be fonned, because pins from both components may map to a common wire. If S' = rename(r)(S). we define D' (c, a) to be rCn(e, a)] if n(c, a) E A; otherwise n' (c, a) n(c, a). All other aspects of the structure remain unchanged.

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