By Michael Lange, Tony Field (auth.), Ana Lucia Varbanescu, Anca Molnos, Rob van Nieuwpoort (eds.)
This booklet constitutes the completely refereed post-conference court cases of the workshops held on the thirty seventh foreign Symposium on machine structure, ISCA 2010, in Saint-Malo, France, in June 2010. The 28 revised complete papers offered have been conscientiously reviewed and chosen from the lectures given at five of those workshops. The papers deal with subject matters starting from novel reminiscence architectures to rising program layout and function research and encompassed the subsequent workshops: A4MMC, functions for multi- and many-cores; AMAS-BT, third workshop on architectural and micro-architectural help for binary translation; EAMA, the third Workshop for rising functions and many-core architectures; WEED, second Workshop on strength effective layout, in addition to WIOSCA, the yearly workshop at the interplay among working platforms and computing device architecture.
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Extra info for Computer Architecture: ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised Selected Papers
Similarly, the copied agent will be written to memory in one block due to the write-back property of the cache. On the other hand, searching through all agents whilst inspecting only one variable will be very ineﬃcient since each agent is still loaded anyway. However, once the simulation contains more agents than the L2 cache can hold, each agent will be read multiple times during the Merge process(O(n2 )), resulting in poor cache performance. The size of the PPE’s L2 cache therefore poses the main hardware limitation.
Ainsworth et al.  conclude that among other factors that constrain the usage of Cell’s Element Interconnect Bus (EIB), such as the control structure, also the concrete communication pattern leads to performance diﬀerences of the same order. Sudheer et al.  discuss the inﬂuence of thread-SPE mapping for large messages. Their conclusions support our intuition that random thread assignments on SPEs can impact both performance and predictability signiﬁcantly. L. Varbanescu et al. ): ISCA 2010 Workshops, LNCS 6161, pp.
We therefore decided to run a set of experiments on a Cell BE processor with a synthetic benchmark application where the tasks communicate in a bidirectional ring. Our ﬁndings are that the mapping is of importance already for small packet sizes, and that the application has little chance to ﬁnd a mapping with best performance, even when actively inﬂuencing the mapping. The remainder of this article is organized as follows. In Sect. 2 we give the necessary details about the Cell BE processor and our synthetic benchmark application.