By Olivier Jamin
This e-book discusses the trade-offs serious about designing direct RF digitization receivers for the radio frequency and electronic sign processing domain names. A system-level framework is built, quantifying the appropriate impairments of the sign processing chain, via a entire system-level research. designated concentration is given to noise research (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion research, together with the effect of the sampling method (low-pass, band-pass), research of time-interleaved ADC channel mismatches, sampling clock purity and electronic channel choice. The system-level framework defined is utilized to the layout of a cable multi-channel RF direct digitization receiver. An optimal RF sign conditioning, and a few algorithms (automatic achieve keep an eye on loop, RF front-end amplitude equalization regulate loop) are used to chill the necessities of a 2.7GHz 11-bit ADC.
A two-chip implementation is gifted, utilizing BiCMOS and 65nm CMOS procedures, including the block and system-level size effects. Readers will enjoy the concepts provided, that are hugely aggressive, either when it comes to rate and RF functionality, whereas greatly decreasing strength consumption.
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Extra resources for Broadband Direct RF Digitization Receivers
39 provides a principle diagram of such a receiver : after external RF band selection, the LNA provides the RF signal to a quadrature sampler, which down-converts the RF signal to IF, and provides anti-aliasing protection and sampling rate reduction prior to analog-todigital conversion. Channel selection is typically performed using DSP techniques. The potential down-conversion of interferers with LO harmonics that is encountered in CT receivers is replaced by the aliasing of interferers due to sampling rate reduction in DT receivers.
This allows scaling down the area and power of stages through the pipeline, down to a limit where parasitic capacitors dominate. 18) i¼1 Each stage necessitates Li comparators: where Bi are the significant bits, and ri bits are reserved for the over-range, with ri The 1st stage of the delta-sigma prototype is transferred to RF using an up-mixer. In addition, an N-path frequency translation technique is used to build a filter at the 26 1 RF Receiver Architecture State of the Art Mixer Bandselect filter LNA VGA 0Њ 90Њ Sampler ADC To demodulator LO 90Њ Fig. 35 Low-IF receiver (left: complex baseband; right: real baseband) RF frf frf+2xfif1 LO IF flo complex bandpass filter fif1 Fig. 36 Signal processing operations in a low-IF receiver first stage (gm1) output.
The 1st stage of the delta-sigma prototype is transferred to RF using an up-mixer. In addition, an N-path frequency translation technique is used to build a filter at the 26 1 RF Receiver Architecture State of the Art Mixer Bandselect filter LNA VGA 0Њ 90Њ Sampler ADC To demodulator LO 90Њ Fig. 35 Low-IF receiver (left: complex baseband; right: real baseband) RF frf frf+2xfif1 LO IF flo complex bandpass filter fif1 Fig. 36 Signal processing operations in a low-IF receiver first stage (gm1) output.